mirror of https://github.com/m-labs/artiq.git
test: fix test_dma
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@ -57,7 +57,7 @@ def do_dma(dut, address):
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yield
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yield
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while ((yield from dut.enable.read())):
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while ((yield from dut.enable.read())):
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yield
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yield
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error = yield from dut.cri_master.underflow.read()
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error = yield from dut.cri_master.error.read()
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if error & 1:
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if error & 1:
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raise RTIOUnderflow
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raise RTIOUnderflow
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if error & 2:
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if error & 2:
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