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phaser: elaborate init sequence, more tests
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f0959fb871
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@ -145,16 +145,17 @@ class Phaser:
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raise ValueError("invalid board id")
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delay(20*us) # slack
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# allow a few errors during startup and alignment
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# allow a few errors during startup and alignment since boot
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if self.get_crc_err() > 20:
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raise ValueError("large number of CRC errors")
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raise ValueError("large number of frame CRC errors")
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delay(.1*ms) # slack
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# reset
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self.set_cfg(dac_resetb=0, att0_rstn=0, att1_rstn=0)
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self.set_leds(0x00)
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self.set_fan_mu(0)
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self.set_cfg(clk_sel=clk_sel) # bring everything out of reset
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self.set_sync_dly(4) # tune?
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self.set_sync_dly(4) # TODO: tune this?
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delay(.1*ms) # slack
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# 4 wire SPI, sif4_enable
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@ -163,7 +164,7 @@ class Phaser:
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raise ValueError("DAC version readback invalid")
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delay(.1*ms)
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if self.dac_read(0x00) != 0x049c:
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raise ValueError("DAC config0 readback invalid")
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raise ValueError("DAC config0 reset readback invalid")
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delay(.1*ms)
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t = self.get_dac_temperature()
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@ -178,8 +179,9 @@ class Phaser:
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[0x7a7a, 0xb6b6, 0xeaea, 0x4545], # ds pattern a
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[0x1a1a, 0x1616, 0xaaaa, 0xc6c6], # ds pattern b
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]
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# A data delay of 2*50 ps heuristically matches FPGA+board+DAC skews.
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# There is plenty of margin and no need to tune at runtime.
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# A data delay of 2*50 ps heuristically and reproducibly matches
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# FPGA+board+DAC skews. There is plenty of margin (>= 250 ps
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# either side) and no need to tune at runtime.
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# Parity provides another level of safety.
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for dly in [-2]: # range(-7, 8)
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if dly < 0:
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@ -188,10 +190,9 @@ class Phaser:
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for i in range(len(patterns)):
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errors = self.dac_iotest(patterns[i])
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if errors:
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raise ValueError("iotest error")
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raise ValueError("DAC iotest failure")
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delay(.5*ms)
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delay(.5*ms) # slack
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self.dac_write(0x00, 0x019c) # I=2, fifo, clkdiv_sync, qmc off
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self.dac_write(0x01, 0x040e) # fifo alarms, parity
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self.dac_write(0x02, 0x70a2) # clk alarms, sif4, nco off, mix, mix_gain, 2s
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@ -226,20 +227,33 @@ class Phaser:
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delay(.1*ms) # slack
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for ch in range(2):
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channel = self.channel[ch]
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# test attenuator write and readback
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self.channel[ch].set_att_mu(0x5a)
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if self.channel[ch].get_att_mu() != 0x5a:
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channel.set_att_mu(0x5a)
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if channel.get_att_mu() != 0x5a:
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raise ValueError("attenuator test failed")
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delay(.1*ms)
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self.channel[ch].set_att(31.5*dB)
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channel.set_att(31.5*dB)
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# dac test data readback
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dac_test = [0x10102020, 0x30304040]
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self.channel[ch].set_duc_cfg(select=1)
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self.channel[ch].set_dac_test(dac_test[ch])
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if self.channel[ch].get_dac_data() != dac_test[ch]:
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raise ValueError("DAC test data readback failed")
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for i in range(len(channel.oscillator)):
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oscillator = channel.oscillator[i]
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if i == 0:
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asf = 0x7fff
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else:
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asf = 0
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# pi/4 phase
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oscillator.set_amplitude_phase_mu(asf=asf, pow=0x2000, clr=1)
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delay_mu(8)
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delay(1*us) # settle link, pipeline and impulse response
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# test oscillator and DUC and their phase sign
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channel.set_duc_phase_mu(0)
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channel.set_duc_cfg(select=0, clr=1)
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self.duc_stb()
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data = channel.get_dac_data()
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delay(.1*ms)
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if data != 0x4a124a12:
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print(data)
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raise ValueError("DUC+oscillator phase/amplitude test failed")
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# self.dac_write(0x20, 0x0000) # stop fifo sync
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# alarm = self.get_sta() & 1
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@ -501,9 +515,14 @@ class Phaser:
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self.dac_write(0x29 + addr, pattern[addr])
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delay(.1*ms)
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for ch in range(2):
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self.channel[ch].set_duc_cfg(select=1) # test
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channel = self.channel[ch]
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channel.set_duc_cfg(select=1) # test
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# dac test data is i msb, q lsb
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self.channel[ch].set_dac_test(pattern[2*ch] | (pattern[2*ch + 1] << 16))
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data = pattern[2*ch] | (pattern[2*ch + 1] << 16)
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channel.set_dac_test(data)
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if channel.get_dac_data() != data:
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raise ValueError("DAC test data readback failed")
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delay(.1*ms)
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self.dac_write(0x01, 0x8000) # iotest_ena
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self.dac_write(0x04, 0x0000) # clear iotest_result
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delay(.2*ms) # let it rip
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