mirror of https://github.com/m-labs/artiq.git
test: relax TTL timing requirements to support DIO EEM
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@ -59,9 +59,10 @@ class AnalyzerTest(ExperimentCase):
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input_messages = [msg for msg in dump.messages
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if isinstance(msg, InputMessage)]
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self.assertEqual(len(input_messages), 2)
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# on Kasli systems, this has to go through the isolated DIO card
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self.assertAlmostEqual(
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abs(input_messages[0].timestamp - input_messages[1].timestamp),
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1000, delta=1)
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1000, delta=4)
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def test_rtio_log(self):
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core_host = self.device_mgr.get_desc("core")["arguments"]["host"]
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@ -379,8 +379,9 @@ class CoredeviceTest(ExperimentCase):
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self.execute(Loopback)
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rtt = self.dataset_mgr.get("rtt")
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print(rtt)
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self.assertGreater(rtt, 0*ns)
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self.assertLess(rtt, 140*ns)
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self.assertGreater(rtt, 20*ns)
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# on Kasli systems, this has to go through the isolated DIO card
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self.assertLess(rtt, 170*ns)
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def test_clock_generator_loopback(self):
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self.execute(ClockGeneratorLoopback)
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