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test: relax TTL timing requirements to support DIO EEM

This commit is contained in:
Sebastien Bourdeauducq 2018-08-17 13:35:16 +08:00
parent 1ba12e1cdb
commit d707d2f4fe
2 changed files with 5 additions and 3 deletions
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3
artiq/test/coredevice/test_analyzer.py
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@ -59,9 +59,10 @@ class AnalyzerTest(ExperimentCase):
input_messages = [msg for msg in dump.messages input_messages = [msg for msg in dump.messages
if isinstance(msg, InputMessage)] if isinstance(msg, InputMessage)]
self.assertEqual(len(input_messages), 2) self.assertEqual(len(input_messages), 2)
# on Kasli systems, this has to go through the isolated DIO card
self.assertAlmostEqual( self.assertAlmostEqual(
abs(input_messages[0].timestamp - input_messages[1].timestamp), abs(input_messages[0].timestamp - input_messages[1].timestamp),
1000, delta=1) 1000, delta=4)
def test_rtio_log(self): def test_rtio_log(self):
core_host = self.device_mgr.get_desc("core")["arguments"]["host"] core_host = self.device_mgr.get_desc("core")["arguments"]["host"]

5
artiq/test/coredevice/test_rtio.py
View File

@ -379,8 +379,9 @@ class CoredeviceTest(ExperimentCase):
self.execute(Loopback) self.execute(Loopback)
rtt = self.dataset_mgr.get("rtt") rtt = self.dataset_mgr.get("rtt")
print(rtt) print(rtt)
self.assertGreater(rtt, 0*ns) self.assertGreater(rtt, 20*ns)
self.assertLess(rtt, 140*ns) # on Kasli systems, this has to go through the isolated DIO card
self.assertLess(rtt, 170*ns)
def test_clock_generator_loopback(self): def test_clock_generator_loopback(self):
self.execute(ClockGeneratorLoopback) self.execute(ClockGeneratorLoopback)