test: relax TTL timing requirements to support DIO EEM

artiq/test/coredevice/test_analyzer.py

@@ -59,9 +59,10 @@ class AnalyzerTest(ExperimentCase):
         input_messages = [msg for msg in dump.messages
                           if isinstance(msg, InputMessage)]
         self.assertEqual(len(input_messages), 2)
+        # on Kasli systems, this has to go through the isolated DIO card
         self.assertAlmostEqual(
             abs(input_messages[0].timestamp - input_messages[1].timestamp),
-            1000, delta=1)
+            1000, delta=4)
 
     def test_rtio_log(self):
         core_host = self.device_mgr.get_desc("core")["arguments"]["host"]

artiq/test/coredevice/test_rtio.py

@@ -379,8 +379,9 @@ class CoredeviceTest(ExperimentCase):
         self.execute(Loopback)
         rtt = self.dataset_mgr.get("rtt")
         print(rtt)
-        self.assertGreater(rtt, 0*ns)
-        self.assertLess(rtt, 140*ns)
+        self.assertGreater(rtt, 20*ns)
+        # on Kasli systems, this has to go through the isolated DIO card
+        self.assertLess(rtt, 170*ns)
 
     def test_clock_generator_loopback(self):
         self.execute(ClockGeneratorLoopback)