M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-26 03:38:25 +08:00
Code Issues Projects Releases Wiki Activity

miqro: name register constants

Browse Source
This commit is contained in:
Robert Jördens 2022-09-02 15:55:28 +00:00
parent 0df2cadcd3
commit d6d0c2c866
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
artiq/coredevice/phaser.py
View File

@ -48,8 +48,8 @@ PHASER_ADDR_SERVO_CFG1 = 0x31
PHASER_ADDR_SERVO_DATA_BASE = 0x32 PHASER_ADDR_SERVO_DATA_BASE = 0x32
# 0x78 Miqro channel profile/window memories # 0x78 Miqro channel profile/window memories
PHASER_ADDR_MIQRO_ADDR = 0x78 PHASER_ADDR_MIQRO_MEM_ADDR = 0x78
PHASER_ADDR_MIQRO_DATA = 0x7a PHASER_ADDR_MIQRO_MEM_DATA = 0x7a
PHASER_SEL_DAC = 1 << 0 PHASER_SEL_DAC = 1 << 0
PHASER_SEL_TRF0 = 1 << 1 PHASER_SEL_TRF0 = 1 << 1
@ -1286,9 +1286,9 @@ class Miqro:
@kernel @kernel
def write8(self, addr, data): def write8(self, addr, data):
self.channel.phaser.write16(PHASER_ADDR_MIQRO_ADDR, self.channel.phaser.write16(PHASER_ADDR_MIQRO_MEM_ADDR,
(self.channel.index << 13) | addr) (self.channel.index << 13) | addr)
self.channel.phaser.write8(PHASER_ADDR_MIQRO_DATA, data) self.channel.phaser.write8(PHASER_ADDR_MIQRO_MEM_DATA, data)
@kernel @kernel
def write32(self, addr, data): def write32(self, addr, data):