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wrpll: collector code modifications from Weida

This commit is contained in:
Sebastien Bourdeauducq 2020-01-13 20:42:41 +08:00
parent 9d7196bdb7
commit d685619bcd
1 changed files with 34 additions and 4 deletions
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38
artiq/gateware/drtio/wrpll/ddmtd.py
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@ -1,5 +1,6 @@
from migen import * from migen import *
from migen.genlib.cdc import PulseSynchronizer, MultiReg from migen.genlib.cdc import PulseSynchronizer, MultiReg
from migen.genlib.fsm import FSM
from misoc.interconnect.csr import * from misoc.interconnect.csr import *
@ -117,9 +118,38 @@ class Collector(Module):
# # # # # #
last_tag_main = Signal(N) fsm = FSM()
self.submodules += fsm
tag_collector = Signal(N)
fsm.act("IDLE",
If(self.tag_main_update & self.tag_helper_update,
NextValue(tag_collector, 0),
NextState("IDLE")
).Elif(self.tag_main_update,
NextValue(tag_collector, self.tag_main),
NextState("WAITHELPER")
).Elif(self.tag_helper_update,
NextValue(tag_collector, -self.tag_helper),
NextState("WAITMAIN")
)
)
fsm.act("WAITHELPER",
If(self.tag_helper_update,
NextValue(tag_collector, tag_collector - self.tag_helper),
NextState("IDLE")
)
)
fsm.act("WAITMAIN",
If(self.tag_main_update,
NextValue(tag_collector, tag_collector + self.tag_main),
NextState("IDLE")
)
)
self.sync += [ self.sync += [
If(self.tag_main_update, last_tag_main.eq(self.tag_main)), self.output_update.eq(0),
self.output_update.eq(self.tag_helper_update), If(self.tag_helper_update,
self.output.eq(last_tag_main - self.tag_helper) self.output_update.eq(1),
self.output.eq(tag_collector)
)
] ]