From d644e982c8c039d1de8237365ca31057c31c22ca Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 19 Mar 2022 22:50:54 +0800 Subject: [PATCH] RELEASE_NOTES: update --- RELEASE_NOTES.rst | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/RELEASE_NOTES.rst b/RELEASE_NOTES.rst index de797aaff..a14fafd11 100644 --- a/RELEASE_NOTES.rst +++ b/RELEASE_NOTES.rst @@ -13,31 +13,35 @@ Highlights: - HVAMP_8CH 8 channel HV amplifier for Fastino / Zotinos - Almazny mezzanine board for Mirny * Softcore targets now use the RISC-V architecture (VexRiscv) instead of OR1K (mor1kx). +* Gateware FPU is supported on KC705 and Kasli 2.0. * Faster compilation for large arrays/lists. * Phaser: - Improved documentation - Expose the DAC coarse mixer and ``sif_sync`` - Exposes upconverter calibration and enabling/disabling of upconverter LO & RF outputs. - Add helpers to align Phaser updates to the RTIO timeline (``get_next_frame_mu()``) -* ``get()``, ``get_mu()``, ``get_att()``, and ``get_att_mu()`` functions added for AD9910 and AD9912 +* Core device moninj is now proxied via the ``aqctl_moninj_proxy`` controller. +* The configuration entry ``rtio_clock`` supports multiple clocking settings, deprecating the usage + of compile-time options. +* Packaging via Nix Flakes. +* Firmware and gateware can now be built on-demand on the M-Labs server using ``afws_client`` + (subscribers only). +* Extended Kasli gateware JSON description with configuration for SPI over DIO. +* ``get()``, ``get_mu()``, ``get_att()``, and ``get_att_mu()`` functions added for AD9910 and AD9912. * On Kasli, the number of FIFO lanes in the scalable events dispatcher (SED) can now be configured in the JSON hardware description file. * ``artiq_ddb_template`` generates edge-counter keys that start with the key of the corresponding TTL device (e.g. ``ttl_0_counter`` for the edge counter on TTL device ``ttl_0``). * ``artiq_master`` now has an ``--experiment-subdir`` option to scan only a subdirectory of the repository when building the list of experiments. -* The configuration entry ``rtio_clock`` supports multiple clocking settings, deprecating the usage - of compile-time options. -* DRTIO: added support for 100MHz clock. +* Added support for 100MHz RTIO clock in DRTIO. * Previously detected RTIO async errors are reported to the host after each kernel terminates and a warning is logged. The warning is additional to the one already printed in the core device log upon detection of the error. -* Removed worker DB warning for writing a dataset that is also in the archive -* Extended Kasli gateware JSON description with configuration for SPI over DIO. - See: https://github.com/m-labs/artiq/pull/1800 +* Removed worker DB warning for writing a dataset that is also in the archive. * ``PCA9548`` I2C switch class renamed to ``I2CSwitch``, to accomodate support for PCA9547, and possibly other switches in future. Readback has been removed, and now only one channel per - switch is supported. + switch is supported. Breaking changes: @@ -51,7 +55,6 @@ Breaking changes: * Phaser: fixed coarse mixer frequency configuration * Mirny: Added extra delays in ``ADF5356.sync()``. This avoids the need of an extra delay before calling `ADF5356.init()`. -* DRTIO: Changed message alignment from 32-bits to 64-bits. * The deprecated ``set_dataset(..., save=...)`` is no longer supported. ARTIQ-6