mirror of https://github.com/m-labs/artiq.git
sayma_rtm: set clock mux pins
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9194402ea5
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@ -81,6 +81,13 @@ class SaymaRTM(Module):
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self.submodules.rtm_identifier = RTMIdentifier()
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self.submodules.rtm_identifier = RTMIdentifier()
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csr_devices.append("rtm_identifier")
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csr_devices.append("rtm_identifier")
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# clock mux: 125MHz ext SMA clock to HMC830 input
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self.comb += [
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platform.request("clk_src_ext_sel").eq(1), # use ext clk from sma
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platform.request("ref_clk_src_sel").eq(1),
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platform.request("dac_clk_src_sel").eq(0), # use clk from dac_clk
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]
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self.submodules.converter_spi = spi.SPIMaster(platform.request("hmc_spi"))
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self.submodules.converter_spi = spi.SPIMaster(platform.request("hmc_spi"))
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csr_devices.append("converter_spi")
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csr_devices.append("converter_spi")
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self.comb += platform.request("hmc7043_reset").eq(0)
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self.comb += platform.request("hmc7043_reset").eq(0)
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