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artiq
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Fixed two too low delay values in Phaser init 

Signed-off-by: Fabian Schwartau <fabian@opencode.eu>
pull/1980/head
Fabian Schwartau 2022-10-19 15:45:45 +02:00
parent 286f151d9a
commit d5e267fadf
1 changed files with 2 additions and 2 deletions
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4
artiq/coredevice/phaser.py
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@ -275,7 +275,7 @@ class Phaser:
for data in self.dac_mmap:
self.dac_write(data >> 16, data)
delay(40*us)
delay(120*us)
self.dac_sync()
delay(40*us)
@ -662,7 +662,7 @@ class Phaser:
.. note:: Synchronising the NCO clears the phase-accumulator
"""
config1f = self.dac_read(0x1f)
delay(.1*ms)
delay(.4*ms)
self.dac_write(0x1f, config1f & ~int32(1 << 1))
self.dac_write(0x1f, config1f | (1 << 1))