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Gateware: frequency multiplier for WRPLL
wrpll: add mmcm with DRP to generate 125Mhz refclk
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@ -171,3 +171,66 @@ class WRPLL(Module, AutoCSR):
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self.submodules.ev = SharedIRQ(self.ref_tag_ev, self.main_tag_ev)
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self.submodules.ev = SharedIRQ(self.ref_tag_ev, self.main_tag_ev)
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class FrequencyMultiplier(Module, AutoCSR):
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def __init__(self, clkin):
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clkin_se = Signal()
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mmcm_locked = Signal()
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mmcm_fb_clk = Signal()
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ref_clk = Signal()
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self.clock_domains.cd_ref = ClockDomain()
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self.refclk_reset = CSRStorage(reset=1)
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self.mmcm_bypass = CSRStorage()
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self.mmcm_locked = CSRStatus()
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self.mmcm_reset = CSRStorage(reset=1)
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self.mmcm_daddr = CSRStorage(7)
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self.mmcm_din = CSRStorage(16)
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self.mmcm_dwen = CSRStorage()
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self.mmcm_den = CSRStorage()
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self.mmcm_dclk = CSRStorage()
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self.mmcm_dout = CSRStatus(16)
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self.mmcm_dready = CSRStatus()
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# # #
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self.specials += [
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Instance("IBUFDS",
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i_I=clkin.p, i_IB=clkin.n,
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o_O=clkin_se),
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# MMCME2 is capable to accept 10MHz input while PLLE2 only support down to 19MHz input (DS191)
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# The MMCME2 can be reconfiged during runtime using the Dynamic Reconfiguration Ports
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Instance("MMCME2_ADV",
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p_BANDWIDTH="HIGH", # lower output jitter (see https://support.xilinx.com/s/question/0D52E00006iHqRqSAK)
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o_LOCKED=self.mmcm_locked.status,
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i_RST=self.mmcm_reset.storage,
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p_CLKIN1_PERIOD=8, # ns
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i_CLKIN1=clkin_se,
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i_CLKINSEL=1, # 1=CLKIN1 0=CLKIN2
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# VCO @ 1.25GHz
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p_CLKFBOUT_MULT_F=10, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=mmcm_fb_clk, o_CLKFBOUT=mmcm_fb_clk,
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# 125MHz for WRPLL
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p_CLKOUT0_DIVIDE_F=10, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=ref_clk,
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# Dynamic Reconfiguration Ports
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i_DADDR = self.mmcm_daddr.storage,
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i_DI = self.mmcm_din.storage,
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i_DWE = self.mmcm_dwen.storage,
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i_DEN = self.mmcm_den.storage,
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i_DCLK = self.mmcm_dclk.storage,
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o_DO = self.mmcm_dout.status,
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o_DRDY = self.mmcm_dready.status
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),
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Instance("BUFGMUX",
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i_I0=ref_clk,
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i_I1=clkin_se,
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i_S=self.mmcm_bypass.storage,
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o_O=self.cd_ref.clk
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),
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AsyncResetSynchronizer(self.cd_ref, self.refclk_reset.storage),
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]
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