mirror of https://github.com/m-labs/artiq.git
aqctl_corelog: add simulation mode
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@ -16,6 +16,8 @@ def get_argparser():
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parser = argparse.ArgumentParser(
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description="ARTIQ controller for core device logs")
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simple_network_args(parser, 1068)
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parser.add_argument("--simulation", action="store_true",
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help="Simulation - does not connect to device")
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parser.add_argument("core_addr", metavar="CORE_ADDR",
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help="hostname or IP address of the core device")
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return parser
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@ -26,6 +28,12 @@ class PingTarget:
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return True
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async def get_logs_sim(host):
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while True:
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await asyncio.sleep(2)
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log_with_name("firmware.simulation", logging.INFO, "hello " + host)
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async def get_logs(host):
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reader, writer = await asyncio.open_connection(host, 1380)
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writer.write(b"ARTIQ management\n")
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@ -59,7 +67,8 @@ def main():
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loop = asyncio.get_event_loop()
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try:
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get_logs_task = asyncio.ensure_future(get_logs(args.core_addr))
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get_logs_task = asyncio.ensure_future(
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get_logs_sim(args.core_addr) if args.simulation else get_logs(args.core_addr))
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try:
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server = Server({"corelog": PingTarget()}, None, True)
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loop.run_until_complete(server.start(bind_address_from_args(args), args.port))
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