M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-28 20:53:35 +08:00
Code Issues Projects Releases Wiki Activity

aqctl_corelog: add simulation mode

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2019-04-19 23:42:37 +08:00
parent 62e9b2d85e
commit d4781e9a8a
1 changed files with 10 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
artiq/frontend/aqctl_corelog.py
View File

@ -16,6 +16,8 @@ def get_argparser():
parser = argparse.ArgumentParser(
description="ARTIQ controller for core device logs")
simple_network_args(parser, 1068)
parser.add_argument("--simulation", action="store_true",
help="Simulation - does not connect to device")
parser.add_argument("core_addr", metavar="CORE_ADDR",
help="hostname or IP address of the core device")
return parser
@ -26,6 +28,12 @@ class PingTarget:
return True
async def get_logs_sim(host):
while True:
await asyncio.sleep(2)
log_with_name("firmware.simulation", logging.INFO, "hello " + host)
async def get_logs(host):
reader, writer = await asyncio.open_connection(host, 1380)
writer.write(b"ARTIQ management\n")
@ -59,7 +67,8 @@ def main():
loop = asyncio.get_event_loop()
try:
get_logs_task = asyncio.ensure_future(get_logs(args.core_addr))
get_logs_task = asyncio.ensure_future(
get_logs_sim(args.core_addr) if args.simulation else get_logs(args.core_addr))
try:
server = Server({"corelog": PingTarget()}, None, True)
loop.run_until_complete(server.start(bind_address_from_args(args), args.port))