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manual: minor fixes to DRTIO doc

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Sebastien Bourdeauducq 2017-06-05 13:26:56 +08:00
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doc/manual/drtio.rst
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Distributed Real Time Input/Output (DRTIO)
==========================================
DRTIO is a time and data transfer system that allows ARTIQ RTIO channels to be distributed among several satellite devices synchronized and controlled by a central master device.
DRTIO is a time and data transfer system that allows ARTIQ RTIO channels to be distributed among several satellite devices synchronized and controlled by a central core device.
The link is a high speed duplex serial line operating at 1Gbps or more, over copper or optical fiber. Time transfer and clock recovery may be done over the serial link alone, or assisted by auxiliary signals. The DRTIO system shall be organized as much as possible to support porting to different types of transceivers (Xilinx MGTs, Altera MGTs, soft transceivers running off regular FPGA IOs, etc.) and different synchronization mechanisms.
The link is a high speed duplex serial line operating at 1Gbps or more, over copper or optical fiber.
The main source of DRTIO traffic is the remote control of RTIO output and input channels. The protocol shall be optimized to maximize throughput and minimize latency, and shall handle flow control and error conditions (underflows, overflows, etc.)
The main source of DRTIO traffic is the remote control of RTIO output and input channels. The protocol is optimized to maximize throughput and minimize latency, and handles flow control and error conditions (underflows, overflows, etc.)
The DRTIO protocol shall also support auxiliary, low-priority and non-realtime traffic. The auxiliary channel shall support overriding and monitoring TTL I/Os. Auxiliary traffic shall never interrupt or delay the main traffic, so that it cannot cause unexpected poor performance (e.g. RTIO underflows).
The DRTIO protocol also supports auxiliary, low-priority and non-realtime traffic. The auxiliary channel supports overriding and monitoring TTL I/Os. Auxiliary traffic never interrupts or delays the main traffic, so that it cannot cause unexpected poor performance (e.g. RTIO underflows).
Time transfer and clock syntonization is typically done over the serial link alone. The DRTIO code is organized as much as possible to support porting to different types of transceivers (Xilinx MGTs, Altera MGTs, soft transceivers running off regular FPGA IOs, etc.) and different synchronization mechanisms.
The lower layers of DRTIO are similar to White Rabbit, with the following main differences: