mirror of https://github.com/m-labs/artiq.git
parent
ced5b938db
commit
d3297df745
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@ -91,7 +91,7 @@ mod imp {
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unsafe {
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csr::rtio::target_write(target as u32);
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// writing target clears o_data
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for i in 0..data.len() {
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for i in (0..data.len()).rev() {
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rtio_o_data_write(i, data[i] as _)
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}
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let status = csr::rtio::o_status_read();
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