From d29ec224976e3f0a673953e9326ac36963f060d1 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 3 Jan 2017 20:03:55 +0100 Subject: [PATCH] remove stale phaser startup kernel --- artiq/examples/phaser/startup_kernel.py | 72 ------------------------- 1 file changed, 72 deletions(-) delete mode 100644 artiq/examples/phaser/startup_kernel.py diff --git a/artiq/examples/phaser/startup_kernel.py b/artiq/examples/phaser/startup_kernel.py deleted file mode 100644 index 085bd913c..000000000 --- a/artiq/examples/phaser/startup_kernel.py +++ /dev/null @@ -1,72 +0,0 @@ -from artiq.experiment import * -from artiq.coredevice.ad9516_reg import * - - -class StartupKernel(EnvExperiment): - def build(self): - self.setattr_device("core") - self.setattr_device("led") - self.setattr_device("ad9154") - - @kernel - def run(self): - self.ad9154.jesd_enable(0) - self.ad9154.init() - self.clock_setup() - - @kernel - def clock_setup(self): - # reset - self.ad9154.clock_write(AD9516_SERIAL_PORT_CONFIGURATION, - AD9516_SOFT_RESET | AD9516_SOFT_RESET_MIRRORED | - AD9516_LONG_INSTRUCTION | AD9516_LONG_INSTRUCTION_MIRRORED | - AD9516_SDO_ACTIVE | AD9516_SDO_ACTIVE_MIRRORED) - self.ad9154.clock_write(AD9516_SERIAL_PORT_CONFIGURATION, - AD9516_LONG_INSTRUCTION | AD9516_LONG_INSTRUCTION_MIRRORED | - AD9516_SDO_ACTIVE | AD9516_SDO_ACTIVE_MIRRORED) - if self.ad9154.clock_read(AD9516_PART_ID) != 0x41: - raise ValueError("AD9516 not found") - - # use clk input, dclk=clk/2 - self.ad9154.clock_write(AD9516_PFD_AND_CHARGE_PUMP, 1*AD9516_PLL_POWER_DOWN | - 0*AD9516_CHARGE_PUMP_MODE) - self.ad9154.clock_write(AD9516_VCO_DIVIDER, 0) - self.ad9154.clock_write(AD9516_INPUT_CLKS, 0*AD9516_SELECT_VCO_OR_CLK | - 0*AD9516_BYPASS_VCO_DIVIDER) - - self.ad9154.clock_write(AD9516_OUT0, 2*AD9516_OUT0_POWER_DOWN) - self.ad9154.clock_write(AD9516_OUT2, 2*AD9516_OUT2_POWER_DOWN) - self.ad9154.clock_write(AD9516_OUT3, 2*AD9516_OUT3_POWER_DOWN) - self.ad9154.clock_write(AD9516_OUT4, 2*AD9516_OUT4_POWER_DOWN) - self.ad9154.clock_write(AD9516_OUT5, 2*AD9516_OUT5_POWER_DOWN) - self.ad9154.clock_write(AD9516_OUT8, 1*AD9516_OUT8_POWER_DOWN) - - # DAC deviceclk, clk/1 - self.ad9154.clock_write(AD9516_DIVIDER_0_2, AD9516_DIVIDER_0_DIRECT_TO_OUTPUT) - self.ad9154.clock_write(AD9516_OUT1, 0*AD9516_OUT1_POWER_DOWN | - 2*AD9516_OUT1_LVPECLDIFFERENTIAL_VOLTAGE) - - # FPGA deviceclk, dclk/1 - self.ad9154.clock_write(AD9516_DIVIDER_4_3, 0*AD9516_DIVIDER_4_NOSYNC | - 1*AD9516_DIVIDER_4_BYPASS_1 | 1*AD9516_DIVIDER_4_BYPASS_2) - self.ad9154.clock_write(AD9516_DIVIDER_4_4, 0*AD9516_DIVIDER_4_DCCOFF) - self.ad9154.clock_write(AD9516_OUT9, 1*AD9516_OUT9_LVDS_OUTPUT_CURRENT | - 2*AD9516_OUT9_LVDS_CMOS_OUTPUT_POLARITY | - 0*AD9516_OUT9_SELECT_LVDS_CMOS) - - # sysref f_data*S/(K*F), dclk/16 - self.ad9154.clock_write(AD9516_DIVIDER_3_0, (16//2-1)*AD9516_DIVIDER_3_HIGH_CYCLES_1 | - (16//2-1)*AD9516_DIVIDER_3_LOW_CYCLES_1) - self.ad9154.clock_write(AD9516_DIVIDER_3_1, 0*AD9516_DIVIDER_3_PHASE_OFFSET_1 | - 0*AD9516_DIVIDER_3_PHASE_OFFSET_2) - self.ad9154.clock_write(AD9516_DIVIDER_3_3, 0*AD9516_DIVIDER_3_NOSYNC | - 0*AD9516_DIVIDER_3_BYPASS_1 | 1*AD9516_DIVIDER_3_BYPASS_2) - self.ad9154.clock_write(AD9516_DIVIDER_3_4, 0*AD9516_DIVIDER_3_DCCOFF) - self.ad9154.clock_write(AD9516_OUT6, 1*AD9516_OUT6_LVDS_OUTPUT_CURRENT | - 2*AD9516_OUT6_LVDS_CMOS_OUTPUT_POLARITY | - 0*AD9516_OUT6_SELECT_LVDS_CMOS) - self.ad9154.clock_write(AD9516_OUT7, 1*AD9516_OUT7_LVDS_OUTPUT_CURRENT | - 2*AD9516_OUT7_LVDS_CMOS_OUTPUT_POLARITY | - 0*AD9516_OUT7_SELECT_LVDS_CMOS) - - self.ad9154.clock_write(AD9516_UPDATE_ALL_REGISTERS, 1)