M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

hmc830: compile-time configurable reference frequency

This commit is contained in:
Sebastien Bourdeauducq 2018-06-19 13:47:32 +08:00
parent 6f3ed81626
commit d29b3dd588
2 changed files with 9 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
artiq/firmware/libboard_artiq/hmc830_7043.rs
View File

@ -330,7 +330,13 @@ pub fn init() -> Result<(), &'static str> {
hmc830::select_spi_mode(); hmc830::select_spi_mode();
hmc830::detect()?; hmc830::detect()?;
hmc830::init(); hmc830::init();
hmc830::set_dividers(1, 24, 0, 2); // 100MHz ref, 1.2GHz out
// 1.2GHz out
#[cfg(hmc830_ref = "100")]
hmc830::set_dividers(1, 24, 0, 2);
#[cfg(hmc830_ref = "150")]
hmc830::set_dividers(2, 32, 0, 2);
hmc830::check_locked()?; hmc830::check_locked()?;
hmc7043::enable(); hmc7043::enable();

2
artiq/gateware/targets/sayma_amc.py
View File

@ -204,6 +204,8 @@ class Standalone(MiniSoC, AMPSoC):
self.submodules += serwb_core self.submodules += serwb_core
self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus) self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
self.config["HMC830_REF"] = "100"
# RTIO # RTIO
rtio_channels = [] rtio_channels = []
for i in range(4): for i in range(4):