diff --git a/doc/manual/fpga_board_ports.rst b/doc/manual/fpga_board_ports.rst
index 13ba6b54a..442c3e691 100644
--- a/doc/manual/fpga_board_ports.rst
+++ b/doc/manual/fpga_board_ports.rst
@@ -13,20 +13,24 @@ The low-cost Pipistrello FPGA board can be used as a lower-cost but slower alter
 
 When plugged to an adapter, the NIST QC1 hardware can be used. The TTL lines are mapped to RTIO channels as follows:
 
-+--------------+----------+-----------------+
-| RTIO channel | TTL line | Capability      |
-+==============+==========+=================+
-| 0            | PMT0     | Input only      |
-+--------------+----------+-----------------+
-| 1            | PMT1     | Input only      |
-+--------------+----------+-----------------+
-| 2-18         | TTL0-16  | Output only     |
-+--------------+----------+-----------------+
-| 19-21        | LEDs     | Output only     |
-+--------------+----------+-----------------+
-| 22           | TTL2     | Output only     |
-+--------------+----------+-----------------+
++--------------+----------+------------+
+| RTIO channel | TTL line | Capability |
++==============+==========+============+
+| 0            | PMT0     | Input      |
++--------------+----------+------------+
+| 1            | PMT1     | Input      |
++--------------+----------+------------+
+| 2-17         | TTL0-15  | Output     |
++--------------+----------+------------+
+| 18           | EXT_LED  | Output     |
++--------------+----------+------------+
+| 19           | USER_LED | Output     |
++--------------+----------+------------+
+| 20           | DDS      | Output     |
++--------------+----------+------------+
 
 The input only limitation on channels 0 and 1 comes from the QC-DAQ adapter. When the adapter is not used (and physically unplugged from the Pipistrello board), the corresponding pins on the Pipistrello can be used as outputs. Do not configure these channels as outputs when the adapter is plugged, as this would cause electrical contention.
 
-The board can accept an external RTIO clock connected to PMT2.
+The board can accept an external RTIO clock connected to PMT2. If the DDS box
+does not drive the PMT2 pair, use XTRIG and patch the XTRIG transciever output
+on the adapter board onto C:15 disconnecting PMT2.
diff --git a/soc/targets/artiq_pipistrello.py b/soc/targets/artiq_pipistrello.py
index 80b647785..fbbb8d270 100644
--- a/soc/targets/artiq_pipistrello.py
+++ b/soc/targets/artiq_pipistrello.py
@@ -83,6 +83,8 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
         self.submodules.leds = gpio.GPIOOut(Cat(
             platform.request("user_led", 0),
             platform.request("user_led", 1),
+            platform.request("user_led", 2),
+            platform.request("user_led", 3),
         ))
 
         self.comb += [
@@ -107,7 +109,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
 
-        phy = ttl_simple.Output(platform.request("user_led", 2))
+        phy = ttl_simple.Output(platform.request("user_led", 4))
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))