From d1a7c1c3a10949420892e47f39326fccbd15f2b9 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Sun, 19 Nov 2017 14:36:20 +0100 Subject: [PATCH] sayma_amc_standalone: connect sawg to jesd again --- artiq/gateware/targets/sayma_amc_standalone.py | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc_standalone.py b/artiq/gateware/targets/sayma_amc_standalone.py index 81c7fb235..f037273e1 100755 --- a/artiq/gateware/targets/sayma_amc_standalone.py +++ b/artiq/gateware/targets/sayma_amc_standalone.py @@ -92,18 +92,11 @@ class AD9154(Module, AutoCSR): def __init__(self, platform, sys_crg, jesd_crg, dac): self.submodules.jesd = AD9154JESD(platform, sys_crg, jesd_crg, dac) - self.sawgs = [sawg.Channel(width=16, parallelism=8) for i in range(8)] + self.sawgs = [sawg.Channel(width=16, parallelism=4) for i in range(4)] self.submodules += self.sawgs - for i in range(len(self.sawgs)): - self.sawgs[i].connect_y(self.sawgs[i ^ 1]) - - # FIXME - #for conv, ch in zip( - # self.jesd.core0.sink.flatten() + - # self.jesd.core1.sink.flatten(), - # self.sawgs): - # self.sync.jesd += conv.eq(Cat(ch.o)) + for conv, ch in zip(self.jesd.core.sink.flatten(), self.sawgs): + self.sync.jesd += conv.eq(Cat(ch.o)) class SaymaAMCStandalone(MiniSoC, AMPSoC):