mirror of https://github.com/m-labs/artiq.git
kasli: v2 clocking WIP, remove SFP LEDs from RTIO
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parent
9bc43b2dbf
commit
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@ -32,7 +32,10 @@ class _RTIOCRG(Module, AutoCSR):
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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clk_synth = platform.request("si5324_clkout_fabric")
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if platform.hw_rev == "v2.0":
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clk_synth = platform.request("cdr_clk_clean_fabric")
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else:
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clk_synth = platform.request("si5324_clkout_fabric")
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clk_synth_se = Signal()
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clk_synth_se = Signal()
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platform.add_period_constraint(clk_synth.p, 8.0)
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += [
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self.specials += [
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@ -174,11 +177,12 @@ class Tester(StandaloneBase):
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eem.Sampler.add_std(self, 3, 2, ttl_serdes_7series.Output_8X)
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eem.Sampler.add_std(self, 3, 2, ttl_serdes_7series.Output_8X)
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eem.Zotino.add_std(self, 4, ttl_serdes_7series.Output_8X)
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eem.Zotino.add_std(self, 4, ttl_serdes_7series.Output_8X)
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for i in (1, 2):
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if hw_rev in ("v1.0", "v1.1"):
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sfp_ctl = self.platform.request("sfp_ctl", i)
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for i in (1, 2):
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phy = ttl_simple.Output(sfp_ctl.led)
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sfp_ctl = self.platform.request("sfp_ctl", i)
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self.submodules += phy
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phy = ttl_simple.Output(sfp_ctl.led)
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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