From d159d0e901b65647e822a6f65e0183da335dddea Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Mon, 9 Dec 2019 19:47:50 +0800
Subject: [PATCH] sayma_rtm: drive clk_src_ext_sel

---
 artiq/gateware/targets/sayma_rtm.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py
index 02a3afe42..08069d239 100755
--- a/artiq/gateware/targets/sayma_rtm.py
+++ b/artiq/gateware/targets/sayma_rtm.py
@@ -185,6 +185,8 @@ class Satellite(_SatelliteBase):
 
         self.add_rtio(rtio_channels)
 
+        self.comb += platform.request("clk_src_ext_sel").eq(0)
+
         # HMC clock chip and DAC control
         self.comb += [
             platform.request("ad9154_rst_n", 0).eq(1),