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sayma: update fmcdio_vhdci_eem demo

This commit is contained in:
Sebastien Bourdeauducq 2018-07-19 15:47:20 +08:00
parent 8dfcd463aa
commit d152506ecb
1 changed files with 19 additions and 3 deletions
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22
artiq/examples/sayma_master/repository/demo.py
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@ -8,10 +8,15 @@ class Demo(EnvExperiment):
self.setattr_device("fmcdio_dirctl") self.setattr_device("fmcdio_dirctl")
self.ttls = [self.get_device("ttl" + str(i)) for i in range(8)] self.ttls = [self.get_device("ttl" + str(i)) for i in range(8)]
self.setattr_device("urukul0_cpld")
self.urukul_chs = [self.get_device("urukul0_ch" + str(i)) for i in range(4)]
self.setattr_device("zotino0")
self.dirctl_word = ( self.dirctl_word = (
shiftreg_bits(2, dio_bank0_out_pins) | shiftreg_bits(1, urukul_out_pins) |
shiftreg_bits(2, dio_bank1_out_pins)) shiftreg_bits(0, urukul_aux_out_pins) |
shiftreg_bits(2, dio_bank0_out_pins | dio_bank1_out_pins) |
shiftreg_bits(3, zotino_out_pins))
@kernel @kernel
def run(self): def run(self):
@ -20,6 +25,17 @@ class Demo(EnvExperiment):
self.fmcdio_dirctl.set(self.dirctl_word) self.fmcdio_dirctl.set(self.dirctl_word)
delay(10*ms) delay(10*ms)
self.urukul0_cpld.init()
delay(10*ms)
self.zotino0.init()
delay(1*ms)
for i in range(32):
self.zotino0.write_dac(i, i/4)
delay(1*ms)
while True: while True:
for ttl in self.ttls: for ttl in self.ttls:
ttl.pulse(1*ms) ttl.pulse(100*ms)
for urukul_ch in self.urukul_chs:
urukul_ch.sw.pulse(100*ms)