From d0b881868832b1f04b75fd2d50a6dbcae3018888 Mon Sep 17 00:00:00 2001 From: Egor Savkin Date: Thu, 13 Apr 2023 11:06:53 +0800 Subject: [PATCH] Add 125 MHz from 80 MHz reference option to rtio clocking Signed-off-by: Egor Savkin --- artiq/firmware/runtime/rtio_clocking.rs | 20 ++++++++++++++++++++ doc/manual/core_device.rst | 1 + doc/manual/installing.rst | 5 +++-- 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/artiq/firmware/runtime/rtio_clocking.rs b/artiq/firmware/runtime/rtio_clocking.rs index f094e5383..cce5d3b7b 100644 --- a/artiq/firmware/runtime/rtio_clocking.rs +++ b/artiq/firmware/runtime/rtio_clocking.rs @@ -10,6 +10,7 @@ pub enum RtioClock { Int_100, Ext0_Bypass, Ext0_Synth0_10to125, + Ext0_Synth0_80to125, Ext0_Synth0_100to125, Ext0_Synth0_125to125, } @@ -24,6 +25,7 @@ fn get_rtio_clock_cfg() -> RtioClock { Ok("ext0_bypass_125") => RtioClock::Ext0_Bypass, Ok("ext0_bypass_100") => RtioClock::Ext0_Bypass, Ok("ext0_synth0_10to125") => RtioClock::Ext0_Synth0_10to125, + Ok("ext0_synth0_80to125") => RtioClock::Ext0_Synth0_80to125, Ok("ext0_synth0_100to125") => RtioClock::Ext0_Synth0_100to125, Ok("ext0_synth0_125to125") => RtioClock::Ext0_Synth0_125to125, Ok("i") => { @@ -44,6 +46,8 @@ fn get_rtio_clock_cfg() -> RtioClock { warn!("si5324_ext_ref and ext_ref_frequency compile-time options are deprecated. Please use the rtio_clock coreconfig settings instead."); #[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "10.0"))] return RtioClock::Ext0_Synth0_10to125; + #[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "80.0"))] + return RtioClock::Ext0_Synth0_80to125; #[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "100.0"))] return RtioClock::Ext0_Synth0_100to125; #[cfg(all(rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "125.0"))] @@ -110,6 +114,22 @@ fn setup_si5324_pll(cfg: RtioClock) { SI5324_EXT_INPUT ) }, + RtioClock::Ext0_Synth0_80to125 => { // 125 MHz output from 80 MHz CLKINx reference, 611 Hz BW + info!("using 80MHz reference to make 125MHz RTIO clock with PLL"); + ( + si5324::FrequencySettings { + n1_hs : 4, + nc1_ls : 10, + n2_hs : 10, + n2_ls : 250, + n31 : 40, + n32 : 40, + bwsel : 4, + crystal_as_ckin2: false + }, + SI5324_EXT_INPUT + ) + }, RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth info!("using 100MHz reference to make 125MHz RTIO clock with PLL"); ( diff --git a/doc/manual/core_device.rst b/doc/manual/core_device.rst index 6ba064e52..24e9768c0 100644 --- a/doc/manual/core_device.rst +++ b/doc/manual/core_device.rst @@ -175,6 +175,7 @@ KC705 in DRTIO variants and Kasli generates the RTIO clock using a PLL locked ei * ``int_100`` - internal crystal oscillator using PLL, 100 MHz output, * ``int_150`` - internal crystal oscillator using PLL, 150 MHz output, * ``ext0_synth0_10to125`` - external 10 MHz reference using PLL, 125 MHz output, + * ``ext0_synth0_80to125`` - external 80 MHz reference using PLL, 125 MHz output, * ``ext0_synth0_100to125`` - external 100 MHz reference using PLL, 125 MHz output, * ``ext0_synth0_125to125`` - external 125 MHz reference using PLL, 125 MHz output, * ``ext0_bypass``, ``ext0_bypass_125``, ``ext0_bypass_100`` - external clock - with explicit aliases available. diff --git a/doc/manual/installing.rst b/doc/manual/installing.rst index 002cb4004..dcf079949 100644 --- a/doc/manual/installing.rst +++ b/doc/manual/installing.rst @@ -343,8 +343,9 @@ The KC705 may use either an external clock signal, or its internal clock with ex Other options include: - ``ext0_synth0_10to125`` - external 10MHz reference clock used by Si5324 to synthesize a 125MHz RTIO clock, - - ``ext0_synth0_100to125`` - exteral 100MHz reference clock used by Si5324 to synthesize a 125MHz RTIO clock, - - ``ext0_synth0_125to125`` - exteral 125MHz reference clock used by Si5324 to synthesize a 125MHz RTIO clock, + - ``ext0_synth0_80to125`` - external 80MHz reference clock used by Si5324 to synthesize a 125MHz RTIO clock, + - ``ext0_synth0_100to125`` - external 100MHz reference clock used by Si5324 to synthesize a 125MHz RTIO clock, + - ``ext0_synth0_125to125`` - external 125MHz reference clock used by Si5324 to synthesize a 125MHz RTIO clock, - ``int_100`` - internal crystal reference is used by Si5324 to synthesize a 100MHz RTIO clock, - ``int_150`` - internal crystal reference is used by Si5324 to synthesize a 150MHz RTIO clock. - ``ext0_bypass_125`` and ``ext0_bypass_100`` - explicit aliases for ``ext0_bypass``.