mirror of https://github.com/m-labs/artiq.git
firmware: remove useless module.
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@ -1,4 +1,3 @@
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mod slave_fpga {
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use board::{csr, clock};
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use core::slice;
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use byteorder::{ByteOrder, BigEndian};
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@ -72,8 +71,3 @@ mod slave_fpga {
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Ok(())
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}
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}
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pub fn load() -> Result<(), &'static str> {
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slave_fpga::load()
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}
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