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firmware: remove useless module.

This commit is contained in:
whitequark 2018-03-01 01:22:52 +00:00
parent 54984f080b
commit d051cec0dd
1 changed files with 64 additions and 70 deletions
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30
artiq/firmware/libboard_artiq/slave_fpga.rs
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@ -1,17 +1,16 @@
mod slave_fpga { use board::{csr, clock};
use board::{csr, clock}; use core::slice;
use core::slice; use byteorder::{ByteOrder, BigEndian};
use byteorder::{ByteOrder, BigEndian};
const CCLK_BIT: u8 = 1 << 0; const CCLK_BIT: u8 = 1 << 0;
const DIN_BIT: u8 = 1 << 1; const DIN_BIT: u8 = 1 << 1;
const DONE_BIT: u8 = 1 << 2; const DONE_BIT: u8 = 1 << 2;
const INIT_B_BIT: u8 = 1 << 3; const INIT_B_BIT: u8 = 1 << 3;
const PROGRAM_B_BIT: u8 = 1 << 4; const PROGRAM_B_BIT: u8 = 1 << 4;
const GATEWARE: *mut u8 = csr::CONFIG_SLAVE_FPGA_GATEWARE as *mut u8; const GATEWARE: *mut u8 = csr::CONFIG_SLAVE_FPGA_GATEWARE as *mut u8;
unsafe fn shift_u8(data: u8) { unsafe fn shift_u8(data: u8) {
for i in 0..8 { for i in 0..8 {
let mut bits: u8 = PROGRAM_B_BIT; let mut bits: u8 = PROGRAM_B_BIT;
if data & (0x80 >> i) != 0 { if data & (0x80 >> i) != 0 {
@ -23,9 +22,9 @@ mod slave_fpga {
csr::slave_fpga_cfg::out_write(bits | CCLK_BIT); csr::slave_fpga_cfg::out_write(bits | CCLK_BIT);
// clock::spin_us(1); // clock::spin_us(1);
} }
} }
pub fn load() -> Result<(), &'static str> { pub fn load() -> Result<(), &'static str> {
info!("Loading slave FPGA gateware..."); info!("Loading slave FPGA gateware...");
let header = unsafe { slice::from_raw_parts(GATEWARE, 8) }; let header = unsafe { slice::from_raw_parts(GATEWARE, 8) };
@ -71,9 +70,4 @@ mod slave_fpga {
} }
Ok(()) Ok(())
}
}
pub fn load() -> Result<(), &'static str> {
slave_fpga::load()
} }