From cfd2fe862707fed6ebd08be89f3495080fd8c8a7 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Fri, 7 Oct 2016 13:40:45 +0200 Subject: [PATCH] phaser: fix fpga deviceclock divider --- artiq/examples/phaser/startup_kernel.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/examples/phaser/startup_kernel.py b/artiq/examples/phaser/startup_kernel.py index db0c7bdb1..eb310ddf5 100644 --- a/artiq/examples/phaser/startup_kernel.py +++ b/artiq/examples/phaser/startup_kernel.py @@ -49,7 +49,7 @@ class StartupKernel(EnvExperiment): # FPGA deviceclk, dclk/4 self.ad9154.clock_write(AD9516_DIVIDER_4_3, AD9516_DIVIDER_4_BYPASS_2) - self.ad9154.clock_write(AD9516_DIVIDER_0_0, + self.ad9154.clock_write(AD9516_DIVIDER_4_0, (4//2-1)*AD9516_DIVIDER_0_HIGH_CYCLES | (4//2-1)*AD9516_DIVIDER_0_LOW_CYCLES) self.ad9154.clock_write(AD9516_DIVIDER_4_4, 1*AD9516_DIVIDER_4_DCCOFF)