M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

rtio/cri: remove unneeded CSR management

This commit is contained in:
Sebastien Bourdeauducq 2019-01-05 23:40:45 +08:00
parent 2c3510497b
commit cf9447ab77
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
artiq/gateware/rtio/cri.py
View File

@ -121,7 +121,7 @@ class KernelInitiator(Module, AutoCSR):
self.sync += If(self.counter_update.re, self.counter.status.eq(tsc.full_ts_cri)) self.sync += If(self.counter_update.re, self.counter.status.eq(tsc.full_ts_cri))
class CRIDecoder(Module, AutoCSR): class CRIDecoder(Module):
def __init__(self, slaves=2, master=None, mode="async", enable_routing=False): def __init__(self, slaves=2, master=None, mode="async", enable_routing=False):
if isinstance(slaves, int): if isinstance(slaves, int):
slaves = [Interface() for _ in range(slaves)] slaves = [Interface() for _ in range(slaves)]
@ -228,7 +228,7 @@ class CRIInterconnectShared(Module):
self.submodules.decoder = CRIDecoder(slaves, shared, mode, enable_routing) self.submodules.decoder = CRIDecoder(slaves, shared, mode, enable_routing)
def get_csrs(self): def get_csrs(self):
return self.switch.get_csrs() + self.decoder.get_csrs() return self.switch.get_csrs()
class RoutingTableAccess(Module, AutoCSR): class RoutingTableAccess(Module, AutoCSR):