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RELEASE_NOTES: fix rst formatting
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@ -17,28 +17,28 @@ ARTIQ-5
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Highlights:
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* Performance improvements:
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- Faster RTIO event submission (1.5x improvement in pulse rate test)
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See: https://github.com/m-labs/artiq/issues/636
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- Faster compilation times (3 seconds saved on kernel compilation time on a typical
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medium-size experiment)
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See: https://github.com/m-labs/artiq/commit/611bcc4db4ed604a32d9678623617cd50e968cbf
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- Faster RTIO event submission (1.5x improvement in pulse rate test)
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See: https://github.com/m-labs/artiq/issues/636
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- Faster compilation times (3 seconds saved on kernel compilation time on a typical
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medium-size experiment)
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See: https://github.com/m-labs/artiq/commit/611bcc4db4ed604a32d9678623617cd50e968cbf
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* Improved packaging and build system:
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- new continuous integration/delivery infrastructure based on Nix and Hydra,
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providing reproducibility, speed and independence.
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- rolling release process (https://github.com/m-labs/artiq/issues/1326).
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- firmware, gateware and device database templates are automatically built for all
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supported Kasli variants.
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- new JSON description format for generic Kasli systems.
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- Nix packages are now supported.
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- many Conda problems worked around.
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- controllers are now out-of-tree.
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- split packages that enable lightweight applications that communicate with ARTIQ,
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e.g. controllers running on non-x86 single-board computers.
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- new continuous integration/delivery infrastructure based on Nix and Hydra,
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providing reproducibility, speed and independence.
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- rolling release process (https://github.com/m-labs/artiq/issues/1326).
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- firmware, gateware and device database templates are automatically built for all
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supported Kasli variants.
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- new JSON description format for generic Kasli systems.
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- Nix packages are now supported.
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- many Conda problems worked around.
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- controllers are now out-of-tree.
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- split packages that enable lightweight applications that communicate with ARTIQ,
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e.g. controllers running on non-x86 single-board computers.
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* Improved Urukul support:
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- AD9910 RAM mode.
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- Configurable refclk divider and PLL bypass.
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- More reliable phase synchronization at high sample rates.
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- Synchronization calibration data can be read from EEPROM.
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- AD9910 RAM mode.
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- Configurable refclk divider and PLL bypass.
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- More reliable phase synchronization at high sample rates.
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- Synchronization calibration data can be read from EEPROM.
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* A gateware-level input edge counter has been added, which offers higher
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throughput and increased flexibility over the usual TTL input PHYs where
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edge timestamps are not required. See :mod:`artiq.coredevice.edge_counter` for
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