From ceabeb8d84c9ba1fab0eb04a9ea6e4c8335b9c20 Mon Sep 17 00:00:00 2001 From: David Nadlinger Date: Sat, 17 Dec 2022 02:06:22 +0000 Subject: [PATCH] firmware: Fix Si5324 initialisation for satellites Commit 740543d4e28424 had unintentionally broken DRTIO satellites, as si5324::setup is also used there. This imports setup_si5324_as_synthesizer() from artiq-zynq, where the input selection was already explicitly done. GitHub: Fixes #2028. --- artiq/firmware/libboard_artiq/si5324.rs | 4 +- artiq/firmware/runtime/rtio_clocking.rs | 169 +++++++++++++----------- 2 files changed, 96 insertions(+), 77 deletions(-) diff --git a/artiq/firmware/libboard_artiq/si5324.rs b/artiq/firmware/libboard_artiq/si5324.rs index bc4930c96..22b452d54 100644 --- a/artiq/firmware/libboard_artiq/si5324.rs +++ b/artiq/firmware/libboard_artiq/si5324.rs @@ -214,11 +214,9 @@ pub fn bypass(input: Input) -> Result<()> { Ok(()) } -pub fn setup(settings: &FrequencySettings, ext_input: Input) -> Result<()> { +pub fn setup(settings: &FrequencySettings, input: Input) -> Result<()> { let s = map_frequency_settings(settings)?; - // FREE_RUN=1 routes XA/XB to CKIN2. - let input = if settings.crystal_ref { Input::Ckin2 } else { ext_input }; let cksel_reg = match input { Input::Ckin1 => 0b00, Input::Ckin2 => 0b01, diff --git a/artiq/firmware/runtime/rtio_clocking.rs b/artiq/firmware/runtime/rtio_clocking.rs index bd227a5b0..da4d8ad92 100644 --- a/artiq/firmware/runtime/rtio_clocking.rs +++ b/artiq/firmware/runtime/rtio_clocking.rs @@ -130,100 +130,121 @@ const SI5324_EXT_INPUT: si5324::Input = si5324::Input::Ckin2; #[cfg(si5324_as_synthesizer)] fn setup_si5324_as_synthesizer(cfg: RtioClock) { - let si5324_settings = match cfg { + let (si5324_settings, si5324_ref_input) = match cfg { RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW info!("using 10MHz reference to make 125MHz RTIO clock with PLL"); - si5324::FrequencySettings { - n1_hs : 10, - nc1_ls : 4, - n2_hs : 10, - n2_ls : 300, - n31 : 6, - n32 : 6, - bwsel : 4, - crystal_ref: false - } + ( + si5324::FrequencySettings { + n1_hs : 10, + nc1_ls : 4, + n2_hs : 10, + n2_ls : 300, + n31 : 6, + n32 : 6, + bwsel : 4, + crystal_ref: false + }, + SI5324_EXT_INPUT + ) }, RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth info!("using 100MHz reference to make 125MHz RTIO clock with PLL"); - si5324::FrequencySettings { - n1_hs : 10, - nc1_ls : 4, - n2_hs : 10, - n2_ls : 260, - n31 : 52, - n32 : 52, - bwsel : 4, - crystal_ref: false - } + ( + si5324::FrequencySettings { + n1_hs : 10, + nc1_ls : 4, + n2_hs : 10, + n2_ls : 260, + n31 : 52, + n32 : 52, + bwsel : 4, + crystal_ref: false + }, + SI5324_EXT_INPUT + ) }, RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth info!("using 125MHz reference to make 125MHz RTIO clock with PLL"); - si5324::FrequencySettings { - n1_hs : 5, - nc1_ls : 8, - n2_hs : 7, - n2_ls : 360, - n31 : 63, - n32 : 63, - bwsel : 4, - crystal_ref: false - } + ( + si5324::FrequencySettings { + n1_hs : 5, + nc1_ls : 8, + n2_hs : 7, + n2_ls : 360, + n31 : 63, + n32 : 63, + bwsel : 4, + crystal_ref: false + }, + SI5324_EXT_INPUT + ) }, RtioClock::Int_150 => { // 150MHz output, from crystal info!("using internal 150MHz RTIO clock"); - si5324::FrequencySettings { - n1_hs : 9, - nc1_ls : 4, - n2_hs : 10, - n2_ls : 33732, - n31 : 7139, - n32 : 7139, - bwsel : 3, - crystal_ref: true - } + ( + si5324::FrequencySettings { + n1_hs : 9, + nc1_ls : 4, + n2_hs : 10, + n2_ls : 33732, + n31 : 7139, + n32 : 7139, + bwsel : 3, + crystal_ref: true + }, + si5324::Input::Ckin2 + ) }, - RtioClock::Int_100 => { // 100MHz output, from crystal. Also used as reference for Sayma HMC830. + RtioClock::Int_100 => { // 100MHz output, from crystal info!("using internal 100MHz RTIO clock"); - si5324::FrequencySettings { - n1_hs : 9, - nc1_ls : 6, - n2_hs : 10, - n2_ls : 33732, - n31 : 7139, - n32 : 7139, - bwsel : 3, - crystal_ref: true - } + ( + si5324::FrequencySettings { + n1_hs : 9, + nc1_ls : 6, + n2_hs : 10, + n2_ls : 33732, + n31 : 7139, + n32 : 7139, + bwsel : 3, + crystal_ref: true + }, + si5324::Input::Ckin2 + ) }, RtioClock::Int_125 => { // 125MHz output, from crystal, 7 Hz info!("using internal 125MHz RTIO clock"); - si5324::FrequencySettings { - n1_hs : 10, - nc1_ls : 4, - n2_hs : 10, - n2_ls : 19972, - n31 : 4565, - n32 : 4565, - bwsel : 4, - crystal_ref: true - } - } + ( + si5324::FrequencySettings { + n1_hs : 10, + nc1_ls : 4, + n2_hs : 10, + n2_ls : 19972, + n31 : 4565, + n32 : 4565, + bwsel : 4, + crystal_ref: true + }, + si5324::Input::Ckin2 + ) + }, _ => { // 125MHz output like above, default (if chosen option is not supported) warn!("rtio_clock setting '{:?}' is not supported. Falling back to default internal 125MHz RTIO clock.", cfg); - si5324::FrequencySettings { - n1_hs : 10, - nc1_ls : 4, - n2_hs : 10, - n2_ls : 19972, - n31 : 4565, - n32 : 4565, - bwsel : 4, - crystal_ref: true - } + ( + si5324::FrequencySettings { + n1_hs : 10, + nc1_ls : 4, + n2_hs : 10, + n2_ls : 19972, + n31 : 4565, + n32 : 4565, + bwsel : 4, + crystal_ref: true + }, + si5324::Input::Ckin2 + ) } }; - si5324::setup(&si5324_settings, SI5324_EXT_INPUT).expect("cannot initialize Si5324"); + si5324::setup(&si5324_settings, si5324_ref_input).expect("cannot initialize Si5324"); } pub fn init() {