diff --git a/artiq/gateware/suservo/dds_ser.py b/artiq/gateware/suservo/dds_ser.py
index 7a53f352e..38d1f6d94 100644
--- a/artiq/gateware/suservo/dds_ser.py
+++ b/artiq/gateware/suservo/dds_ser.py
@@ -2,6 +2,8 @@ import logging
 
 from migen import *
 
+from artiq.coredevice.urukul import DEFAULT_PROFILE
+
 from . import spi
 
 
@@ -26,7 +28,8 @@ class DDS(spi.SPISimple):
 
         self.profile = [Signal(32 + 16 + 16, reset_less=True)
                 for i in range(params.channels)]
-        cmd = Signal(8, reset=0x15)  # write to single tone profile 7
+        # write to single tone default profile
+        cmd = Signal(8, reset=0x0e + DEFAULT_PROFILE)
         assert params.width == len(cmd) + len(self.profile[0])
 
         self.sync += [