M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

serwb: fix case when rtm fpga is not loaded, lvds input can be 0 or 1

This commit is contained in:
Florent Kermarrec 2018-05-11 23:31:25 +02:00
parent 2e3bf8602f
commit cd4477864a
2 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
artiq/gateware/serwb/kusphy.py
View File

@ -215,4 +215,5 @@ class KUSSerdes(Module):
idle_timer = WaitTimer(32)
self.submodules += idle_timer
self.comb += idle_timer.wait.eq(1)
self.sync += self.rx_idle.eq(idle_timer.done & (rx_bitslip.o == 0))
self.sync += self.rx_idle.eq(idle_timer.done &
((rx_bitslip.o == 0) | (rx_bitslip.o == (2**40-1))))

3
artiq/gateware/serwb/s7phy.py
View File

@ -226,4 +226,5 @@ class S7Serdes(Module):
idle_timer = WaitTimer(32)
self.submodules += idle_timer
self.comb += idle_timer.wait.eq(1)
self.sync += self.rx_idle.eq(idle_timer.done & (rx_bitslip.o == 0))
self.sync += self.rx_idle.eq(idle_timer.done &
((rx_bitslip.o == 0) | (rx_bitslip.o == (2**40-1))))