mirror of https://github.com/m-labs/artiq.git
gateware/spi: fix import
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@ -2,7 +2,7 @@ from itertools import product
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from migen import *
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from migen import *
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from misoc.interconnect import wishbone
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from misoc.interconnect import wishbone
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from misoc.cores.spi.core import SPIMachine
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from misoc.cores.spi import SPIMachine
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class SPIMaster(Module):
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class SPIMaster(Module):
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