coredevice.ad9910: Fix phase tracking ref_time passing

This is difficult to test without hardware mocks or some
form of phase readback, but the symptom was that e.g.
`self.dds.set(…, ref_time=now_mu() - 1)` would fail
periodically, that is, whenever bit 32 of the timestamp
would be set (which would be turned into the sign bit).

This is a fairly sinister issue, and is probably a compiler
bug of some sort (either accepts-invalid or wrong type inference).

artiq/coredevice/ad9910.py

@@ -256,9 +256,11 @@ class AD9910:
         self.write32(_AD9910_REG_CFR1, 0x00000002 | (bits << 4))
         self.cpld.io_update.pulse(1*us)
 
+    # KLUDGE: ref_time default argument is explicitly marked int64() to avoid
+    # silent truncation of explicitly passed timestamps. (Compiler bug?)
     @kernel
     def set_mu(self, ftw, pow=0, asf=0x3fff, phase_mode=_PHASE_MODE_DEFAULT,
-               ref_time=-1, profile=0):
+               ref_time=int64(-1), profile=0):
         """Set profile 0 data in machine units.
 
         This uses machine units (FTW, POW, ASF). The frequency tuning word
@@ -336,7 +338,7 @@ class AD9910:
 
     @kernel
     def set(self, frequency, phase=0.0, amplitude=1.0,
-            phase_mode=_PHASE_MODE_DEFAULT, ref_time=-1, profile=0):
+            phase_mode=_PHASE_MODE_DEFAULT, ref_time=int64(-1), profile=0):
         """Set profile 0 data in SI units.
 
         .. seealso:: :meth:`set_mu`