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artiq
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Commit missing parts of 9366a29.

This commit is contained in:
whitequark 2016-01-10 13:08:26 +00:00
parent 9366a29483
commit cc45694f5a
2 changed files with 10 additions and 7 deletions
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6
artiq/coredevice/core.py
View File

@ -38,15 +38,15 @@ def rtio_get_counter() -> TInt64:
raise NotImplementedError("syscall not simulated") raise NotImplementedError("syscall not simulated")
@syscall @syscall
def cache_get(TStr) -> TList(TInt32): def cache_get(key: TStr) -> TList(TInt32):
raise NotImplementedError("syscall not simulated") raise NotImplementedError("syscall not simulated")
@syscall @syscall
def cache_put(TStr, TList(TInt32)): def cache_put(key: TStr, value: TList(TInt32)):
raise NotImplementedError("syscall not simulated") raise NotImplementedError("syscall not simulated")
@syscall @syscall
def cache_clear(TStr): def cache_clear(key: TStr):
raise NotImplementedError("syscall not simulated") raise NotImplementedError("syscall not simulated")
class Core: class Core:

3
artiq/runtime/session.c
View File

@ -1036,10 +1036,13 @@ static int process_kmsg(struct msg_base *umsg)
} }
if(!row->borrowed) { if(!row->borrowed) {
if(request->length != 0) {
row->length = request->length; row->length = request->length;
row->elements = calloc(row->length, sizeof(int32_t)); row->elements = calloc(row->length, sizeof(int32_t));
memcpy(row->elements, request->elements, memcpy(row->elements, request->elements,
sizeof(int32_t) * row->length); sizeof(int32_t) * row->length);
}
reply.succeeded = 1; reply.succeeded = 1;
} else { } else {
reply.succeeded = 0; reply.succeeded = 0;