From cc45694f5a3802b2cc872ccb27eaddafc36a9069 Mon Sep 17 00:00:00 2001 From: whitequark Date: Sun, 10 Jan 2016 13:08:26 +0000 Subject: [PATCH] Commit missing parts of 9366a29. --- artiq/coredevice/core.py | 6 +++--- artiq/runtime/session.c | 11 +++++++---- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/artiq/coredevice/core.py b/artiq/coredevice/core.py index 7d0b379c2..bd8483098 100644 --- a/artiq/coredevice/core.py +++ b/artiq/coredevice/core.py @@ -38,15 +38,15 @@ def rtio_get_counter() -> TInt64: raise NotImplementedError("syscall not simulated") @syscall -def cache_get(TStr) -> TList(TInt32): +def cache_get(key: TStr) -> TList(TInt32): raise NotImplementedError("syscall not simulated") @syscall -def cache_put(TStr, TList(TInt32)): +def cache_put(key: TStr, value: TList(TInt32)): raise NotImplementedError("syscall not simulated") @syscall -def cache_clear(TStr): +def cache_clear(key: TStr): raise NotImplementedError("syscall not simulated") class Core: diff --git a/artiq/runtime/session.c b/artiq/runtime/session.c index fddf41781..a41002a02 100644 --- a/artiq/runtime/session.c +++ b/artiq/runtime/session.c @@ -1036,10 +1036,13 @@ static int process_kmsg(struct msg_base *umsg) } if(!row->borrowed) { - row->length = request->length; - row->elements = calloc(row->length, sizeof(int32_t)); - memcpy(row->elements, request->elements, - sizeof(int32_t) * row->length); + if(request->length != 0) { + row->length = request->length; + row->elements = calloc(row->length, sizeof(int32_t)); + memcpy(row->elements, request->elements, + sizeof(int32_t) * row->length); + } + reply.succeeded = 1; } else { reply.succeeded = 0;