M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-28 20:53:35 +08:00
Code Issues Projects Releases Wiki Activity

Commit missing parts of 9366a29.

Browse Source
This commit is contained in:
whitequark 2016-01-10 13:08:26 +00:00
parent 9366a29483
commit cc45694f5a
2 changed files with 10 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
artiq/coredevice/core.py
View File

@ -38,15 +38,15 @@ def rtio_get_counter() -> TInt64:
raise NotImplementedError("syscall not simulated")
@syscall
def cache_get(TStr) -> TList(TInt32):
def cache_get(key: TStr) -> TList(TInt32):
raise NotImplementedError("syscall not simulated")
@syscall
def cache_put(TStr, TList(TInt32)):
def cache_put(key: TStr, value: TList(TInt32)):
raise NotImplementedError("syscall not simulated")
@syscall
def cache_clear(TStr):
def cache_clear(key: TStr):
raise NotImplementedError("syscall not simulated")
class Core:

11
artiq/runtime/session.c
View File

@ -1036,10 +1036,13 @@ static int process_kmsg(struct msg_base *umsg)
}
if(!row->borrowed) {
row->length = request->length;
row->elements = calloc(row->length, sizeof(int32_t));
memcpy(row->elements, request->elements,
sizeof(int32_t) * row->length);
if(request->length != 0) {
row->length = request->length;
row->elements = calloc(row->length, sizeof(int32_t));
memcpy(row->elements, request->elements,
sizeof(int32_t) * row->length);
}
reply.succeeded = 1;
} else {
reply.succeeded = 0;