From cb8815cc65cac4caa1e8108f81bc9590e53f63a8 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Mon, 29 Feb 2016 16:44:04 +0100 Subject: [PATCH] Revert "gateware/rt2wb: support combinatorial ack" This reverts commit f73228f248fa2ce5d29a906dfc4973b913a1881a. --- artiq/gateware/rtio/phy/wishbone.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/artiq/gateware/rtio/phy/wishbone.py b/artiq/gateware/rtio/phy/wishbone.py index 4eb69ceed..429e2c8ce 100644 --- a/artiq/gateware/rtio/phy/wishbone.py +++ b/artiq/gateware/rtio/phy/wishbone.py @@ -23,9 +23,6 @@ class RT2WB(Module): active = Signal() self.sync.rio += [ - If(active & wb.ack, - active.eq(0), - ), If(self.rtlink.o.stb, active.eq(1), wb.adr.eq(self.rtlink.o.address[:address_width]), @@ -33,11 +30,15 @@ class RT2WB(Module): wb.dat_w.eq(self.rtlink.o.data), wb.sel.eq(2**len(wb.sel) - 1) ), + If(wb.ack, + active.eq(0) + ) ] self.comb += [ - self.rtlink.o.busy.eq(active & ~wb.ack), + self.rtlink.o.busy.eq(active), wb.cyc.eq(active), wb.stb.eq(active), + self.rtlink.i.stb.eq(active & wb.ack & ~wb.we), self.rtlink.i.data.eq(wb.dat_r) ]