From cb6e44b23a85428710af205a6f1c155eda7b2443 Mon Sep 17 00:00:00 2001 From: hartytp Date: Mon, 11 Jun 2018 21:19:57 +0100 Subject: [PATCH] Sayma: disable unused HMC7043 outputs. --- artiq/firmware/libboard_artiq/hmc830_7043.rs | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs index bc4e94e9b..dbbf1409b 100644 --- a/artiq/firmware/libboard_artiq/hmc830_7043.rs +++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs @@ -142,7 +142,6 @@ mod hmc830 { pub mod hmc7043 { use board_misoc::csr; - // To do: check which output channels we actually need const DAC_CLK_DIV: u32 = 2; const FPGA_CLK_DIV: u32 = 8; const SYSREF_DIV: u32 = 128; @@ -156,11 +155,11 @@ pub mod hmc7043 { (true, SYSREF_DIV, 0x0, 0x0), // 3: DAC1_SYSREF (false, 0, 0x0, 0x0), // 4: ADC2_CLK (false, 0, 0x0, 0x0), // 5: ADC2_SYSREF - (true, FPGA_CLK_DIV, 0x0, 0x0), // 6: GTP_CLK2 + (false, 0, 0x0, 0x0), // 6: GTP_CLK2 (true, SYSREF_DIV, 0x0, 0x0), // 7: FPGA_DAC_SYSREF (true, FPGA_CLK_DIV, 0x0, 0x0), // 8: GTP_CLK1 - (true, FPGA_CLK_DIV, 0x0, 0x0), // 9: AMC_MASTER_AUX_CLK - (true, FPGA_CLK_DIV, 0x0, 0x0), // 10: RTM_MASTER_AUX_CLK + (false, 0, 0x0, 0x0), // 9: AMC_MASTER_AUX_CLK + (false, 0, 0x0, 0x0), // 10: RTM_MASTER_AUX_CLK (false, 0, 0x0, 0x0), // 11: FPGA_ADC_SYSREF (false, 0, 0x0, 0x0), // 12: ADC1_CLK (false, 0, 0x0, 0x0), // 13: ADC1_SYSREF