mirror of https://github.com/m-labs/artiq.git
use new misoc identifier
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1568e55388
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@ -5,7 +5,7 @@ extern crate byteorder;
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#[macro_use]
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#[macro_use]
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extern crate log;
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extern crate log;
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use core::{cmp, ptr, str};
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use core::{cmp, str};
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include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/mem.rs"));
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include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/mem.rs"));
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include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/csr.rs"));
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include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/csr.rs"));
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@ -45,11 +45,13 @@ pub use uart_console::Console;
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pub fn ident(buf: &mut [u8]) -> &str {
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pub fn ident(buf: &mut [u8]) -> &str {
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unsafe {
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unsafe {
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let len = ptr::read_volatile(csr::IDENTIFIER_MEM_BASE);
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csr::identifier::address_write(0);
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let len = cmp::min(len as usize, buf.len());
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let len = csr::identifier::data_read();
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let len = cmp::min(len, buf.len() as u8);
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for i in 0..len {
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for i in 0..len {
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buf[i] = ptr::read_volatile(csr::IDENTIFIER_MEM_BASE.offset(1 + i as isize)) as u8
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csr::identifier::address_write(1 + i);
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buf[i as usize] = csr::identifier::data_read();
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}
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}
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str::from_utf8_unchecked(&buf[..len])
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str::from_utf8_unchecked(&buf[..len as usize])
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}
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}
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}
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}
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