From cadde970e12fc0ce92a9999987d49f254d62e76c Mon Sep 17 00:00:00 2001 From: David Nadlinger Date: Tue, 8 Jan 2019 02:37:58 +0000 Subject: [PATCH] urukul: Expand CPLD sync_sel explanation [nfc] --- artiq/coredevice/urukul.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/artiq/coredevice/urukul.py b/artiq/coredevice/urukul.py index 8c8ee340a..620eaf7da 100644 --- a/artiq/coredevice/urukul.py +++ b/artiq/coredevice/urukul.py @@ -133,8 +133,10 @@ class CPLD: internal MMCX. For hardware revision <= v1.2 valid options are: 0 - either XO or MMCX dependent on component population; 1 SMA. Unsupported clocking options are silently ignored. - :param sync_sel: SYNC_IN selection. 0 corresponds to SYNC_IN over EEM - from FPGA. 1 corresponds to SYNC_IN from DDS0. + :param sync_sel: SYNC (multi-chip synchronisation) signal source selection. + 0 corresponds to SYNC_IN being supplied by the FPGA via the EEM + connector. 1 corresponds to SYNC_OUT from DDS0 being distributed to the + other chips. :param rf_sw: Initial CPLD RF switch register setting (default: 0x0). Knowledge of this state is not transferred between experiments. :param att: Initial attenuator setting shift register (default: