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ad9910: relax timing for faster spi clock

This commit is contained in:
Robert Jördens 2018-01-22 08:12:59 +00:00
parent 0d73401365
commit ca1fdaa190
1 changed files with 3 additions and 3 deletions
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6
artiq/coredevice/ad9910.py
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@ -99,15 +99,15 @@ class AD9910:
aux_dac = self.read32(_AD9910_REG_AUX_DAC) aux_dac = self.read32(_AD9910_REG_AUX_DAC)
if aux_dac & 0xff != 0x7f: if aux_dac & 0xff != 0x7f:
raise ValueError("Urukul AD9910 AUX_DAC mismatch") raise ValueError("Urukul AD9910 AUX_DAC mismatch")
delay(10*us) delay(100*us)
self.write32(_AD9910_REG_CFR2, 0x01400020) self.write32(_AD9910_REG_CFR2, 0x01400020)
cfr3 = (0x0807c100 | (self.pll_vco << 24) | cfr3 = (0x0807c100 | (self.pll_vco << 24) |
(self.pll_cp << 19) | (self.pll_n << 1)) (self.pll_cp << 19) | (self.pll_n << 1))
self.write32(_AD9910_REG_CFR3, cfr3 | 0x400) # PFD reset self.write32(_AD9910_REG_CFR3, cfr3 | 0x400) # PFD reset
delay(10*us) delay(100*us)
self.cpld.io_update.pulse(100*ns) self.cpld.io_update.pulse(100*ns)
self.write32(_AD9910_REG_CFR3, cfr3) self.write32(_AD9910_REG_CFR3, cfr3)
delay(10*us) delay(100*us)
self.cpld.io_update.pulse(100*ns) self.cpld.io_update.pulse(100*ns)
for i in range(100): for i in range(100):
lock = urukul_sta_pll_lock(self.cpld.sta_read()) lock = urukul_sta_pll_lock(self.cpld.sta_read())