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moninj: fix underflows for urukul freq set

This commit is contained in:
mwojcik 2022-07-07 11:24:20 +08:00 committed by Sébastien Bourdeauducq
parent 8be945d5c7
commit c9fb7b410f
1 changed files with 5 additions and 3 deletions
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8
artiq/dashboard/moninj.py
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@ -560,6 +560,7 @@ class _DeviceManager:
if len(cfg) > 0: if len(cfg) > 0:
self.{cpld}.cfg_reg = cfg[0] self.{cpld}.cfg_reg = cfg[0]
else: else:
delay(10*ms)
self.{cpld}.init() self.{cpld}.init()
self.core_cache.put("_{cpld}_cfg", [self.{cpld}.cfg_reg]) self.core_cache.put("_{cpld}_cfg", [self.{cpld}.cfg_reg])
cfg = self.core_cache.get("_{cpld}_cfg") cfg = self.core_cache.get("_{cpld}_cfg")
@ -582,8 +583,8 @@ class _DeviceManager:
@kernel @kernel
def run(self): def run(self):
self.core.break_realtime() self.core.reset()
delay(2*ms) delay(5*ms)
{cpld_init} {cpld_init}
self.{dds_channel}.init() self.{dds_channel}.init()
self.{dds_channel}.set({freq}) self.{dds_channel}.set({freq})
@ -612,11 +613,12 @@ class _DeviceManager:
@kernel @kernel
def run(self): def run(self):
self.core.break_realtime() self.core.break_realtime()
delay(2*ms) delay(5*ms)
cfg = self.core_cache.get("_{cpld}_cfg") cfg = self.core_cache.get("_{cpld}_cfg")
if len(cfg) > 0: if len(cfg) > 0:
self.{cpld}.cfg_reg = cfg[0] self.{cpld}.cfg_reg = cfg[0]
else: else:
delay(10*ms)
self.{cpld}.init() self.{cpld}.init()
self.core_cache.put("_{cpld}_cfg", [self.{cpld}.cfg_reg]) self.core_cache.put("_{cpld}_cfg", [self.{cpld}.cfg_reg])
cfg = self.core_cache.get("_{cpld}_cfg") cfg = self.core_cache.get("_{cpld}_cfg")