From c8b9eed9c9a17aecca035a2721e5c26f06f3b39b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Wed, 16 Feb 2022 14:42:22 +0000 Subject: [PATCH] fastino: add comments about sideeffects on v0.1 --- artiq/coredevice/fastino.py | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/artiq/coredevice/fastino.py b/artiq/coredevice/fastino.py index 53d3c6f79..c2ea4ad2c 100644 --- a/artiq/coredevice/fastino.py +++ b/artiq/coredevice/fastino.py @@ -65,6 +65,9 @@ class Fastino: It does not change set channel voltages and does not reset the PLLs or clock domains. + + Note: On Fastino gateware before v0.2 this may lead to 0 voltage being emitted + transiently. """ self.set_cfg(reset=0, afe_power_down=0, dac_clr=0, clr_err=1) delay_mu(self.t_frame) @@ -274,9 +277,12 @@ class Fastino: def apply_cic(self, channel_mask): """Apply the staged interpolator configuration on the specified channels. - Each Fastino channel includes a fourth order (cubic) CIC interpolator with - variable rate change and variable output gain compensation (see - :meth:`stage_cic`). + Each Fastino channel starting with gateware v0.2 includes a fourth order + (cubic) CIC interpolator with variable rate change and variable output + gain compensation (see :meth:`stage_cic`). + + Fastino gateware before v0.2 does not include the interpolators and the + methods affecting the CICs should not be used. Channels using non-unity interpolation rate should have continous DAC updates enabled (see :meth:`set_continuous`) unless