From c8b8f7a4bed7f756e4fd956c25dbfe5350384db1 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 20 Dec 2019 18:58:31 +0800 Subject: [PATCH] sayma_rtm: connect attenuator shift registers in series --- artiq/gateware/targets/sayma_rtm.py | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index 622a3312c..e14195af5 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -183,16 +183,22 @@ class Satellite(_SatelliteBase): phy = ttl_serdes_7series.Output_8X(platform.request("basemod{}_rfsw".format(bm), i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) + print("BaseMod{} attenuator starting at RTIO channel 0x{:06x}" .format(bm, len(rtio_channels))) basemod_att = platform.request("basemod{}_att".format(bm)) - for name in "rst_n clk mosi le".split(): + for name in "rst_n clk le".split(): signal = getattr(basemod_att, name) for i in range(len(signal)): phy = ttl_simple.Output(signal[i]) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - phy = ttl_simple.InOut(basemod_att.miso) + phy = ttl_simple.Output(basemod_att.mosi[0]) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + for i in range(3): + self.comb += basemod_att.mosi[i+1].eq(basemod_att.miso[i]) + phy = ttl_simple.InOut(basemod_att.miso[3]) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy))