From c7de1f2e6bd24abcb5e393f2bf8f706a3da06b5d Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 5 Feb 2020 00:06:34 +0800 Subject: [PATCH] metlino: drive clock muxes --- artiq/gateware/targets/metlino.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/artiq/gateware/targets/metlino.py b/artiq/gateware/targets/metlino.py index 999bfaaf6..65e3c2f0c 100755 --- a/artiq/gateware/targets/metlino.py +++ b/artiq/gateware/targets/metlino.py @@ -53,6 +53,8 @@ class Master(MiniSoC, AMPSoC): platform = self.platform rtio_clk_freq = 150e6 + self.comb += platform.request("input_clk_sel").eq(1) + self.comb += platform.request("filtered_clk_sel").eq(1) self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c")