diff --git a/artiq/frontend/artiq_flash.sh b/artiq/frontend/artiq_flash.sh
index 4d155e4b9..881e5a616 100755
--- a/artiq/frontend/artiq_flash.sh
+++ b/artiq/frontend/artiq_flash.sh
@@ -123,9 +123,13 @@ then
 	PROXY=bscan_spi_kc705.bit
 	BIOS_ADDR=0xaf0000
 	RUNTIME_ADDR=0xb00000
-	RUNTIME_FILE=${MEZZANINE_BOARD}/runtime.fbi
+	RUNTIME_FILE=runtime.fbi
 	FS_ADDR=0xb40000
-	if [ -z "$BIN_PREFIX" ]; then BIN_PREFIX=$ARTIQ_PREFIX/binaries/kc705; fi
+	if [ -z "$BIN_PREFIX" ]
+	then
+		RUNTIME_FILE=${MEZZANINE_BOARD}/runtime.fbi
+		BIN_PREFIX=$ARTIQ_PREFIX/binaries/kc705
+	fi
 	search_for_proxy $PROXY
 elif [ "$BOARD" == "pipistrello" ]
 then
diff --git a/artiq/test/scheduler.py b/artiq/test/scheduler.py
index a3783863e..33e712fb5 100644
--- a/artiq/test/scheduler.py
+++ b/artiq/test/scheduler.py
@@ -1,6 +1,7 @@
 import unittest
 import asyncio
 import sys
+import os
 from time import time, sleep
 
 from artiq import *
@@ -63,7 +64,10 @@ _handlers = {
 
 class SchedulerCase(unittest.TestCase):
     def setUp(self):
-        self.loop = asyncio.new_event_loop()
+        if os.name == "nt":
+            self.loop = asyncio.ProactorEventLoop()
+        else:
+            self.loop = asyncio.new_event_loop()
         asyncio.set_event_loop(self.loop)
 
     def test_steps(self):
diff --git a/artiq/test/worker.py b/artiq/test/worker.py
index abb321e27..b00660188 100644
--- a/artiq/test/worker.py
+++ b/artiq/test/worker.py
@@ -1,6 +1,7 @@
 import unittest
 import asyncio
 import sys
+import os
 from time import sleep
 
 from artiq import *
@@ -59,7 +60,10 @@ def _run_experiment(class_name):
 
 class WatchdogCase(unittest.TestCase):
     def setUp(self):
-        self.loop = asyncio.new_event_loop()
+        if os.name == "nt":
+            self.loop = asyncio.ProactorEventLoop()
+        else:
+            self.loop = asyncio.new_event_loop()
         asyncio.set_event_loop(self.loop)
 
     def test_watchdog_no_timeout(self):
diff --git a/conda/artiq/build.sh b/conda/artiq/build.sh
index f74722cee..098b19d4f 100755
--- a/conda/artiq/build.sh
+++ b/conda/artiq/build.sh
@@ -42,7 +42,7 @@ cd $SRC_DIR/misoc; $PYTHON make.py -X ../soc -t artiq_pipistrello $MISOC_EXTRA_I
 cp soc/runtime/runtime.fbi $BIN_PREFIX/pipistrello/
 cp $SRC_DIR/misoc/software/bios/bios.bin $BIN_PREFIX/pipistrello/
 cp $SRC_DIR/misoc/build/artiq_pipistrello-nist_qc1-pipistrello.bit $BIN_PREFIX/pipistrello/
-wget http://www.phys.ethz.ch/~robertjo/bscan_spi_lx45_csg324.bit
+wget https://people.phys.ethz.ch/~robertjo/bscan_spi_lx45_csg324.bit
 mv bscan_spi_lx45_csg324.bit $BIN_PREFIX/pipistrello/
 
 # build for KC705 NIST_QC2
diff --git a/doc/manual/installing.rst b/doc/manual/installing.rst
index da2b6a893..f97d6f9ee 100644
--- a/doc/manual/installing.rst
+++ b/doc/manual/installing.rst
@@ -176,7 +176,7 @@ These steps are required to generate bitstream (``.bit``) files, build the MiSoC
         ::
 
             $ cd ~/artiq-dev
-            $ wget http://www.phys.ethz.ch/~robertjo/bscan_spi_lx45_csg324.bit
+            $ wget https://people.phys.ethz.ch/~robertjo/bscan_spi_lx45_csg324.bit
 
         Then copy ``~/artiq-dev/bscan_spi_lx45_csg324.bit`` to ``~/.migen``, ``/usr/local/share/migen`` or ``/usr/share/migen``.