From c7b18952b88311457925873eea4df14a51f85106 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 9 Jan 2019 13:47:08 +0800 Subject: [PATCH] sayma_amc: work around Ultrascale LVDS Toutbuf_delay_td_pad --- artiq/gateware/targets/sayma_amc.py | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index efefc2f45..25aa85b90 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -400,6 +400,17 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon): self.csr_devices.append("sysref_sampler") +def workaround_us_lvds_tristate(platform): + # Those shoddy Kintex Ultrascale FPGAs take almost a microsecond to change the direction of a + # LVDS I/O buffer. The application has to cope with it and this cannot be handled at static + # timing analysis. Disable the latter for IOBUFDS. + # See: + # https://forums.xilinx.com/t5/Timing-Analysis/Delay-890-ns-in-OBUFTDS-in-Kintex-UltraScale/td-p/868364 + # FIXME: this is a bit zealous. Xilinx SR in progress to find a more selective command. + platform.add_platform_command( + "set_false_path -through [get_pins -filter {{REF_PIN_NAME == O}} -of [get_cells -filter {{REF_NAME == IOBUFDS}}]]") + + class Master(MiniSoC, AMPSoC): """ DRTIO master with 2 SFP ports plus 8 lanes on RTM. @@ -528,6 +539,7 @@ class Master(MiniSoC, AMPSoC): iostandard="LVDS") eem.Zotino.add_std(self, 3, ttl_simple.Output, iostandard="LVDS") + workaround_us_lvds_tristate(platform) self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)