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rtio: fix guard cycle computation

This commit is contained in:
Sebastien Bourdeauducq 2014-11-30 01:00:52 +08:00
parent 39c4b5416f
commit c78c5a2b4f
1 changed files with 1 additions and 2 deletions
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3
soc/artiqlib/rtio/core.py
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@ -61,10 +61,9 @@ class _RTIOCounter(Module):
# #
# The buffer must be transferred to the FIFO soon enough to account for: # The buffer must be transferred to the FIFO soon enough to account for:
# * transfer of counter to sys domain: Tio + 2*Tsys + Tsys # * transfer of counter to sys domain: Tio + 2*Tsys + Tsys
# * guard time detection latency: Tsys
# * FIFO latency: Tsys + 2*Tio # * FIFO latency: Tsys + 2*Tio
# Therefore we must choose: # Therefore we must choose:
# guard_io_cycles > (3*Tio + 5*Tsys)/Tio # guard_io_cycles > (3*Tio + 4*Tsys)/Tio
# #
# We are writing to the FIFO from the buffer when the guard time has been # We are writing to the FIFO from the buffer when the guard time has been
# reached without checking the FIFO's writable status. If the FIFO is full, # reached without checking the FIFO's writable status. If the FIFO is full,