Rust: port mailbox routines.

artiq/runtime.rs/src/board.rs

@@ -3,6 +3,10 @@ use core::{cmp, ptr, str};
 include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/mem.rs"));
 include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/csr.rs"));
 
+extern {
+    pub fn flush_cpu_dcache();
+}
+
 pub fn ident(buf: &mut [u8]) -> &str {
     unsafe {
         let len = ptr::read_volatile(csr::IDENTIFIER_MEM_BASE);

artiq/runtime.rs/src/lib.rs

@@ -16,6 +16,7 @@ mod sched;
 mod config;
 mod clock;
 mod rtio_crg;
+mod mailbox;
 
 mod logger;
 

artiq/runtime.rs/src/mailbox.rs

@@ -0,0 +1,51 @@
+use core::ptr::{read_volatile, write_volatile};
+use board;
+
+const MAILBOX: *mut u32 = board::mem::MAILBOX_BASE as *mut u32;
+static mut last: u32 = 0;
+
+pub fn send(data: u32) {
+    unsafe {
+        last = data;
+        write_volatile(MAILBOX, data)
+    }
+}
+
+pub fn acknowledged() -> bool {
+    unsafe {
+        let data = read_volatile(MAILBOX);
+        data == 0 || data != last
+    }
+}
+
+pub fn send_and_wait(data: u32) {
+    send(data);
+    while !acknowledged() {}
+}
+
+pub fn receive() -> u32 {
+    unsafe {
+        let data = read_volatile(MAILBOX);
+        if data == last {
+            0
+        } else {
+            if data != 0 {
+                board::flush_cpu_dcache()
+            }
+            data
+        }
+    }
+}
+
+pub fn wait_and_receive() -> u32 {
+    loop {
+        let data = receive();
+        if data != 0 {
+            return data
+        }
+    }
+}
+
+pub fn acknowledge() {
+    unsafe { write_volatile(MAILBOX, 0) }
+}