mirror of https://github.com/m-labs/artiq.git
LLVMIRGenerator: emit debug information.
This commit is contained in:
whitequark
parent
4f02f6e667
commit
c63ec70c53
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@ -3,6 +3,7 @@
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into LLVM intermediate representation.
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"""
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import os
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from pythonparser import ast, diagnostic
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from llvmlite_artiq import ir as ll
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from .. import types, builtins, ir
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@ -14,7 +15,147 @@ lli8 = ll.IntType(8)
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lli32 = ll.IntType(32)
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lldouble = ll.DoubleType()
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llptr = ll.IntType(8).as_pointer()
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llemptyptr = ll.LiteralStructType( []).as_pointer()
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llmetadata = ll.MetaData()
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DW_LANG_Python = 0x0014
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DW_TAG_compile_unit = 17
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DW_TAG_subroutine_type = 21
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DW_TAG_file_type = 41
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DW_TAG_subprogram = 46
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def memoize(generator):
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def memoized(self, *args):
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result = self.cache.get((generator,) + args, None)
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if result is None:
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return generator(self, *args)
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else:
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return result
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return memoized
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class DebugInfoEmitter:
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def __init__(self, llmodule):
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self.llmodule = llmodule
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self.cache = {}
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self.subprograms = []
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def emit(self, operands):
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def map_operand(operand):
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if operand is None:
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return ll.Constant(llmetadata, None)
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elif isinstance(operand, str):
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return ll.MetaDataString(self.llmodule, operand)
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elif isinstance(operand, bool):
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return ll.Constant(lli1, operand)
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elif isinstance(operand, int):
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return ll.Constant(lli32, operand)
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elif isinstance(operand, (list, tuple)):
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return self.emit(operand)
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elif isinstance(operand, ll.Value):
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return operand
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else:
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print(operand)
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assert False
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return self.llmodule.add_metadata(list(map(map_operand, operands)))
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@memoize
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def emit_filename(self, source_buffer):
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source_dir, source_file = os.path.split(source_buffer.name)
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return self.emit([source_file, source_dir])
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@memoize
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def emit_compile_unit(self, source_buffer, llsubprograms):
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return self.emit([
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DW_TAG_compile_unit,
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self.emit_filename(source_buffer), # filename
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DW_LANG_Python, # source language
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"ARTIQ", # producer
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False, # optimized?
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"", # linker flags
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0, # runtime version
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[], # enum types
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[], # retained types
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llsubprograms, # subprograms
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[], # global variables
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[], # imported entities
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"", # split debug filename
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2, # kind (full=1, lines only=2)
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])
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@memoize
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def emit_file(self, source_buffer):
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return self.emit([
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DW_TAG_file_type,
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self.emit_filename(source_buffer), # filename
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])
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@memoize
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def emit_subroutine_type(self, typ):
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return self.emit([
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DW_TAG_subroutine_type,
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None, # filename
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None, # context descriptor
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"", # name
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0, # line number
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0, # (i64) size in bits
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0, # (i64) alignment in bits
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0, # (i64) offset in bits
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0, # flags
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None, # derived from
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[None], # members
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0, # runtime languages
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None, # base type with vtable pointer
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None, # template parameters
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None # unique identifier
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])
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@memoize
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def emit_subprogram(self, func, llfunc):
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source_buffer = func.loc.source_buffer
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display_name = "{}{}".format(func.name, types.TypePrinter().name(func.type))
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subprogram = self.emit([
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DW_TAG_subprogram,
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self.emit_filename(source_buffer), # filename
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self.emit_file(source_buffer), # context descriptor
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func.name, # name
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display_name, # display name
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llfunc.name, # linkage name
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func.loc.line(), # line number where defined
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self.emit_subroutine_type(func.type), # type descriptor
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func.is_internal, # local to compile unit?
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True, # global is defined in the compile unit?
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0, # virtuality
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0, # index into a virtual function
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None, # base type with vtable pointer
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0, # flags
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False, # optimized?
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llfunc, # LLVM function
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None, # template parameters
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None, # function declaration descriptor
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[], # function variables
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func.loc.line(), # line number where scope begins
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])
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self.subprograms.append(subprogram)
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return subprogram
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@memoize
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def emit_loc(self, loc, scope, inlined_scope=None):
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return self.emit([
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loc.line(), # line
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loc.column(), # column
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scope, # scope
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inlined_scope, # inlined scope
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])
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def finalize(self, source_buffer):
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llident = self.llmodule.add_named_metadata('llvm.ident')
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llident.add(self.emit(["ARTIQ"]))
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llflags = self.llmodule.add_named_metadata('llvm.module.flags')
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llflags.add(self.emit([2, "Debug Info Version", 1]))
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llcompile_units = self.llmodule.add_named_metadata('llvm.dbg.cu')
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llcompile_units.add(self.emit_compile_unit(source_buffer, tuple(self.subprograms)))
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class LLVMIRGenerator:
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@ -27,8 +168,8 @@ class LLVMIRGenerator:
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self.llmodule.data_layout = target.data_layout
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self.llfunction = None
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self.llmap = {}
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self.llblock_map = {}
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self.fixups = []
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self.phis = []
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self.debug_info_emitter = DebugInfoEmitter(self.llmodule)
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def llty_of_type(self, typ, bare=False, for_return=False):
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typ = typ.find()
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@ -200,6 +341,9 @@ class LLVMIRGenerator:
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for func in functions:
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self.process_function(func)
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if any(functions):
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self.debug_info_emitter.finalize(functions[0].loc.source_buffer)
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return self.llmodule
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def process_function(self, func):
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@ -219,9 +363,10 @@ class LLVMIRGenerator:
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self.llfunction.attributes.add('uwtable')
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self.llmap = {}
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self.llbuilder = ll.IRBuilder()
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self.fixups = []
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llblock_map = {}
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disubprogram = self.debug_info_emitter.emit_subprogram(func, self.llfunction)
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# First, map arguments.
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for arg, llarg in zip(func.arguments, self.llfunction.args):
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@ -240,27 +385,29 @@ class LLVMIRGenerator:
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assert llinsn is not None
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self.llmap[insn] = llinsn
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if insn.loc is not None:
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diloc = self.debug_info_emitter.emit_loc(insn.loc, disubprogram)
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llinsn.set_metadata('dbg', diloc)
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# There is no 1:1 correspondence between ARTIQ and LLVM
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# basic blocks, because sometimes we expand a single ARTIQ
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# instruction so that the result spans several LLVM basic
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# blocks. This only really matters for phis, which will
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# use a different map.
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self.llblock_map[block] = self.llbuilder.basic_block
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llblock_map[block] = self.llbuilder.basic_block
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# Fourth, fixup phis.
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for fixup in self.fixups:
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fixup()
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# Fourth, add incoming values to phis.
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for phi, llphi in self.phis:
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for value, block in phi.incoming():
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llphi.add_incoming(self.map(value), llblock_map[block])
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finally:
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self.llfunction = None
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self.llmap = None
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self.fixups = []
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self.llmap = {}
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self.llphis = []
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def process_Phi(self, insn):
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llinsn = self.llbuilder.phi(self.llty_of_type(insn.type), name=insn.name)
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def fixup():
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for value, block in insn.incoming():
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llinsn.add_incoming(self.map(value), self.llblock_map[block])
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self.fixups.append(fixup)
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self.phis.append((insn, llinsn))
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return llinsn
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def llindex(self, index):
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@ -793,8 +940,7 @@ class LLVMIRGenerator:
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def process_LandingPad(self, insn):
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# Layout on return from landing pad: {%_Unwind_Exception*, %Exception*}
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lllandingpadty = ll.LiteralStructType([llptr,
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llptr])
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lllandingpadty = ll.LiteralStructType([llptr, llptr])
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lllandingpad = self.llbuilder.landingpad(lllandingpadty,
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self.llbuiltin("__artiq_personality"),
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cleanup=True)
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